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Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment

Data up to Jan 2025

Published2003
Citations52
References19

Total Citations Per Year

Abstract

References (19)

A logic design structure for LSI testability

1977 • 848 citations

An experimental chip to evaluate test techniques experiment results

2002 • 281 citations

Extraction and simulation of realistic CMOS faults using inductive fault analysis

2003 • 253 citations

Defect classes-an overdue paradigm for CMOS IC testing

2002 • 207 citations

Very-low-voltage testing for weak CMOS logic ICs

2002 • 175 citations

IDDQ and AC scan: the war against unmodelled defects

2002 • 146 citations

An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing

2002 • 143 citations

Current signatures [VLSI circuit testing]

2002 • 121 citations

The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?

1992 • 120 citations

Current signatures: application

2002 • 118 citations

Systematic characterization of physical defects for fault analysis of MOS IC cells

1984 • 106 citations

So what is an optimal test mix? A discussion of the SEMATECH methods experiment

2002 • 97 citations

Functional and scan tests: The effectiveness of I/sub DDQ/ how many fault coverages do we need?

1992 • 72 citations

Application and analysis of IDDQ diagnostic software

2002 • 42 citations

Fault Diagnosis in an LSSD Environment.

1981 • 24 citations

Signature analysis for IC diagnosis and failure analysis

2002 • 19 citations

An overview of CMOS VLSI failure analysis and the importance of test and diagnostics

2002 • 17 citations

IC failure analysis tools and techniques-magic, mystery, and science

2002 • 16 citations

Current signatures for integrated circuit test strategy advisor

1998 • 4 citations

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